Method for the formation of fin structures for finfet devices

ABSTRACT

On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer. In a second region, a second semiconductor material region is formed over the sacrificial layer. The first semiconductor material region is patterned to define a first FinFET fin. The second semiconductor material region is patterned to define a second FinFET fin. The fins are each covered with a cap and sidewall spacer. The sacrificial layer formed of the second semiconductor material is then selectively removed to form an opening below each of the first and second FinFET fins (with those fins being supported by the sidewall spacers). The openings below each of the fins are then filled with a dielectric material that serves to isolate the semiconductive materials of the fins from the substrate.

TECHNICAL FIELD

The present invention relates to integrated circuits and, in particular,to a process for the formation of fin structures for use in FinFET-typeintegrated circuit devices.

BACKGROUND

The prior art teaches the formation of integrated circuits which utilizeone or more FinFET type field effect transistors. The FinFET transistorcomprises a channel region which is oriented to conduct an electricalcurrent parallel to the surface of the substrate. The channel region isprovided in an elongated section of semiconductor material. The sourceand drain regions of the transistor are formed in the elongated sectionon either side of the channel region. A gate is placed over and on bothopposed sides of the elongated section at the location of the channelregion to provide control over the conductive state of the transistor.This FinFET design is well suited for manufacturing a multi-channeltransistor in which multiple elongated sections are formed in parallelto define neighboring channel regions which are separated from eachother by an intermediate gate portion of the transistor gate spanningwith a perpendicular orientation over the multiple elongated sections.

A FinFET transistor is created from at least one thin portion (referredto as the “fin”) of semiconductor material defining the elongatedsection which is used to form the channel of the transistor and also itssource and drain zones. This fin is typically defined by a mask that isformed on top of a monocrystalline silicon substrate at the position ofthe fin. The substrate material is then directionally etched where thereis no mask, to a determined depth, such that the elongated sectiondefining the fin remains under the mask and is composed of the substratematerial.

In one prior art implementation, the fin of semiconductor material whichis thus obtained, and which comprises the channel of the finaltransistor, is not electrically insulated from the active portion of thecircuit substrate, which itself is also of crystalline semiconductormaterial. Such a FinFET device suffers from three distinct types ofleakage current. A first type of leakage current can circulate betweenthe source and drain of the finFET transistor, via the active portion ofthe substrate situated below the channel. This first leakage current,internal to each transistor, is not controlled by the potential appliedto the transistor gate. A second type of leakage current arises becausethe channel of the finFET transistor is also in electrical contact withthe channels of other transistors of the same conductivity type via thesubstrate. The second leakage current flows between transistors in theform of an inter-transistor leakage current. A third type of leakagecurrent appears between the channel of each finFET transistor and alower part of the substrate in response to the substrate being connectedto a reference potential.

There is a need in the art for a bulk FinFET configuration whichsuppresses junction leakage between the source and drain.

As CMOS process technology continues to scale towards smaller andsmaller dimensions, further improvement in transistor performance isneeded. Those skilled in the art recognize that the use ofsilicon-germanium (SiGe) materials for transistor fabrication providefor a significant boost in transistor performance, especially withrespect to p-channel field effect transistor devices. Indeed, the art ismoving towards the use of SiGe for p-channel devices of many differenttypes. Specific to the use of FinFET devices, those skilled in artrecognize a need to form the fin of the p-channel device from a SiGematerial in order to reach improved transistor performance levels overprior art Si material only devices.

SUMMARY

In an embodiment, a method comprises: on a substrate formed of a firstsemiconductor material and having a first region and a second region,depositing an overlying sacrificial layer formed of a secondsemiconductor material; forming for the first region a region of firstsemiconductor material over the sacrificial layer; forming for thesecond region a region of second semiconductor material over thesacrificial layer; patterning the region of first semiconductor materialto define at least one first fin of a FinFET transistor of a firstconductivity type; patterning the region of second semiconductormaterial to define at least one second fin of a FinFET transistor of asecond conductivity type; covering each of the first and second finswith a cap and sidewall spacer; selectively removing the sacrificiallayer formed of the second semiconductor material to form an openingbelow each of the first and second fins, each first and second fin beingsupported by said sidewall spacer; and filling the opening below each ofthe first and second fins with a dielectric material so as to isolatethe first and second fins from the substrate.

In an embodiment, an apparatus comprises: a substrate formed of a firstsemiconductor material and having a first region and a second region; inthe first region, a first dielectric pedestal with a trench on oppositesides of the first dielectric pedestal; in the second region, a seconddielectric pedestal with a trench on opposite sides of the seconddielectric pedestal; in the first region, a first fin of a FinFETtransistor of a first conductivity type formed of a first semiconductormaterial over the first dielectric pedestal and insulated from thesubstrate by the first dielectric pedestal; and in the second region, asecond fin of a FinFET transistor of a second conductivity type formedof a second semiconductor material over the second dielectric pedestaland insulated from the substrate by the second dielectric pedestal.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the embodiments, reference will now bemade by way of example only to the accompanying figures in which:

FIGS. 1-18 illustrate process steps in the formation of fins for aFinFET device on a bulk substrate.

DETAILED DESCRIPTION OF THE DRAWINGS

Reference is now made to FIGS. 1-18 which illustrate the process stepsin the formation of fins for a FinFET device on a bulk substrate.

FIG. 1 shows a conventional bulk silicon substrate wafer 10.

Using an epitaxial process tool, an epitaxial growth process as known inthe art is performed to grow a silicon-germanium (SiGe) layer 12 on asilicon substrate 14 of the bulk silicon substrate wafer 10. Thethickness of the silicon-germanium (SiGe) layer 12 is about 10 nm to 30nm. The silicon-germanium (SiGe) layer 12 is a sacrificial layer to bereplaced by an insulative dielectric material as will be described inmore detail below. Without removing the substrate wafer 10 from theepitaxial process tool, an epitaxial growth process as known in the artis then performed to grow a silicon-carbide (SiC) layer 16 on thesilicon-germanium (SiGe) layer 12. The thickness of the silicon-carbide(SiC) layer 16 is about 10 nm to 20 nm. Without removing the substratewafer 10 from the epitaxial process tool, an epitaxial growth process asknown in the art is then performed to grow a silicon (Si) layer 18 onthe silicon-carbide (SiC) layer 16. The thickness of the silicon (Si)layer 18 is about 30 nm to 40 nm. The structure resulting from theforegoing epitaxial growth processes is shown in FIG. 2. The stipplingin FIG. 2 is provided to differentiate SiGe material from Si material.The silicon-germanium (SiGe) layer 12, silicon-carbide (SiC) layer 16and silicon (Si) layer 18 may be doped as needed for the integratedcircuit application.

FIG. 3 shows the deposit of a silicon nitride (SiN) layer 20 over thesilicon (Si) layer 18.

A lithographic process as known in the art is then used to form anopening 22 in the silicon nitride (SiN) layer 20 which extends down toreach at least the top surface of the silicon (Si) layer 18. The resultof the lithographic process is shown in FIG. 4. The opening 22 isassociated with a region 24 of the substrate wafer 10 reserved for theformation of p-channel FinFET devices. The region 26 of the substratewafer 10 is conversely reserved for the formation of n-channel FinFETdevices. Thus, the process described and illustrated primarily concernsthe formation of CMOS type integrated circuits, although it will beunderstood that this is not the only application of the describedprocess. In plan view, the opening 22 may take on any desired shapegoverned by the size and number of p-channel devices to be formed withinthe region 24.

Using an epitaxial process tool, a high pressure directional etchprocess (such as an RIE process) as known in the art is then performedto remove a portion 28 of the silicon (Si) layer 18 within the region 24down to the silicon-carbide (SiC) layer 16. In an embodiment, thedirectional etch may comprise a high pressure HCl etch. The result ofthe directional etch process is shown in FIG. 5.

Without removing the substrate 10 from the epitaxial process tool usedfor the etch of FIG. 5, an epitaxial growth process as known in the artis then performed to grow a silicon-germanium (SiGe) layer 30 on top ofthe silicon-carbide (SiC) layer 16 in region 24 to fill the portion 28of the silicon (Si) layer 18 that was previously removed. The result ofthe epitaxial growth process is shown in FIG. 6. The stippling in FIG. 6is provided to differentiate SiGe material from Si material. Thethickness of the silicon-germanium (SiGe) layer 30 in region 24 ispreferably at least the thickness of the silicon (Si) layer 18 in theadjacent region 26. The silicon nitride (SiN) layer 20 is then removed.

A lithographic process as known in the art is then used to define thefins 150 for the FinFET devices. A lithographic mask of silicon nitride(SiN) 32 is applied over the top surface of the silicon-germanium (SiGe)layer 30 in region 24 and the silicon (Si) layer 18 in region 26. Themask is patterned to leave SiN mask material at the desired locations ofthe fins 150. An etching operation is then performed to open apertures152 in the silicon-germanium (SiGe) layer 30 in region 24 and in thesilicon (Si) layer 18 in region 26 on either side of each fin 150. Theapertures 152 further extend through the silicon-carbide (SiC) layer 16and reach partially into the silicon-germanium (SiGe) layer 12. In apreferred implementation, a portion 34 of the (sacrificial)silicon-germanium (SiGe) layer 12 remains at the bottom of each aperture152. The result of the etching process is shown in FIG. 7. The fins 150include fins 150 p for use in forming p-channel transistors in theregion 24 and fins 150 n for use in forming n-channel transistors in theregion 26. The etching process used to form the fins 150 may, forexample, comprise a Cl₂ or HBr etch as known in the art and may beperformed in multiple etch steps (such as a first etch through to thesilicon-carbide (SiC) layer 16 followed by a second etch through thesilicon-carbide (SiC) layer 16 and into the silicon-germanium (SiGe)layer 12). Even more particularly, the etching process may utilize asidewall image transfer (SIT) process such as that described, forexample, in U.S. Pat. No. 8,298,954, the disclosure of which isincorporated by reference.

Silicon nitride (SiN) is then deposited over the fins 150. The depositedsilicon nitride (SiN) is then etched (for example, using an RIE process)to remove the silicon nitride (SiN) at the portion 34 of the(sacrificial) silicon-germanium (SiGe) layer 12 between the fins 150 andthus define trenches 40 between adjacent fins 150. The result of thesilicon nitride (SiN) deposit and etch process is shown in FIG. 8. Eachfin 150 is now covered by silicon nitride (SiN) in the form of a thicksilicon nitride (SiN) cap 36 and thin silicon nitride (SiN) sidewallspacers 38. The thin silicon nitride (SiN) sidewall spacers 38 have athickness of 3 nm to 10 nm.

The trenches 40 are then filled with silicon dioxide (SiO₂) 44 and aplanarization process (for example, chemical-mechanical polishing(CMP)), is used to flatten the top of the wafer. The polishing processis configured to stop at the silicon nitride (SiN) cap 36. The result ofthe silicon dioxide (SiO₂) deposit and polish process is shown in FIG.9.

Reference is now made to FIG. 10 which illustrates a top view showingthe relationship between a gate (PC) pattern and the fins 150. A PC maskin accordance with the PC pattern of FIG. 10 is applied to the wafer ofFIG. 9 and an anisotropic etch of the silicon dioxide (SiO₂) 44 depositis performed through the PC mask to open trenches 48 through the silicondioxide (SiO₂) 44 deposit to reach the portion 34 of thesilicon-germanium (SiGe) layer 12 which remained at the bottom of eachaperture 152 (see, FIG. 7). The anisotropic etch is continued to extendthrough the silicon-germanium (SiGe) layer 12 and reach partially intothe silicon substrate 14. As a result, trenches 48 are formed onopposite sides a pedestal portion 49 defined in the silicon substrate14.

The result of the anisotropic etch is shown in FIG. 11, whichillustrates a cross-section taken along lines A-A of FIG. 10. FIG. 9illustrates the cross-section taken along lines B-B of FIG. 10.

A conformal silicon nitride (SiN) deposit is then made within each opentrench 48 to cover exposed side surfaces of each fin 150 and the exposedsilicon substrate 14 at the bottom of each open trench 48. The result ofthis deposit is to extend (reference 38′) the thin silicon nitride (SiN)sidewall spacers 38 over the portions of the silicon-germanium (SiGe)layer 12 and silicon substrate 14 exposed by the anisotropic etchperformed in connection with FIGS. 10 and 11 to produce open trenches48. The thin silicon nitride (SiN) sidewall spacers 38 have a thicknessof 6 nm to 12 nm and the extensions 38′ have a thickness of 3 nm to 8nm. The trenches 48 are then filled with silicon dioxide (SiO₂) 54 and aplanarization process (for example, chemical-mechanical polishing(CMP)), is used to flatten the top of the wafer. The polishing processis configured to stop at the silicon nitride (SiN) cap 36. The result ofthe conformal silicon nitride (SiN) deposit, silicon dioxide (SiO₂)deposit and polish process is shown in FIG. 12 (cross-section againtaken along lines A-A of FIG. 10). FIG. 9 illustrates the cross-sectiontaken along lines B-B of FIG. 10.

The previously deposited silicon dioxide (SiO₂) fills (references 44 and54) are then recessed to a depth sufficient to expose thesilicon-germanium (SiGe) layer 12 at locations away from the trenches 48which were filled by silicon dioxide (SiO₂) 54 (see, FIG. 11). In otherwords, the silicon-germanium (SiGe) layer 12 is exposed at thoselocations which were not covered by the thin silicon nitride (SiN)sidewall spacers 38 or extensions 38′. The process to recess is anetching process, for example of a standard dry etch type, to etch SiO₂.The etch is a blanket removal. The etchant may comprise SiCoNi which hasa uniform etch speed across different (dense or loose) areas.

The result of the process to recess the silicon dioxide (SiO₂) 44 and 54is shown in FIG. 13 (cross-section again taken along lines A-A of FIG.10) and FIG. 14 (cross-section taken this time along lines B-B of FIG.10). FIG. 14 shows the locations 56 where the process to recess thesilicon dioxide (SiO₂) 44 and 54 has exposed the underlyingsilicon-germanium (SiGe) layer 12. Additionally, it will be noted thatprocess to recess the silicon dioxide (SiO₂) 44 and 54 does not affectthe silicon nitride (SiN) deposits and thus the fins 150 are protectedin both FIG. 13 and FIG. 14 by the thin silicon nitride (SiN) sidewallspacers 38 and extensions 38′. The extensions 38′ in FIG. 13 furthercover the silicon-germanium (SiGe) layer 12 and silicon (Si) substrate14.

An etch process as known in the art is then performed to selectivelyremove the sacrificial material of the silicon-germanium (SiGe) layer 12through the locations 56 where the silicon-germanium (SiGe) layer 12 isexposed. In an embodiment, the etch may comprise an HCl dry etch whichis selective to remove SiGe and leave the adjacent Si structures inplace. The result of the selective etch process is shown in FIGS. 15 and16 (which correspond to FIGS. 13 and 14, respectively). As a result ofthe removal of the sacrificial silicon-germanium (SiGe) layer 12,apertures 60 are formed at the locations previously occupied by thesacrificial silicon-germanium (SiGe) layer 12. Notwithstanding thepresence of apertures 60 at and under each fin 150, it will berecognized that each fin 150 continues to be structurally supported bythe thin silicon nitride (SiN) sidewall spacers 38 and extensions 38′.

The silicon-carbide (SiC) material underneath the silicon-germanium(SiGe) layer 30 in region 24 serves to protect the silicon-germanium(SiGe) portion of the fins 150 p from being etched away along with thesacrificial material of the silicon-germanium (SiGe) layer 12.

The apertures 60 under and around each fin 150 and the trenches 62between fins 150 (FIGS. 15 and 16) are then filled with a dielectricmaterial such as silicon dioxide (SiO₂) 64 and a planarization process(for example, chemical-mechanical polishing (CMP)), is used to flattenthe top of the wafer. The polishing process is configured to stop at thesilicon nitride (SiN) cap 36. The result of the silicon dioxide (SiO₂)fill and polish process is shown in FIG. 17.

The silicon dioxide (SiO₂) 64 fill between the fins 150 is then recessedto a depth no lower than the bottom of the silicon-carbide (SiC) layer16. The thick silicon nitride (SiN) cap 36 the thin silicon nitride(SiN) sidewall spacers 38 on top of and adjacent to each of the fins 150are also removed. The result of the recess and removal process is shownin FIG. 18 wherein individual fins 150 are formed. The fins include fins150 p made of silicon-germanium from silicon-germanium (SiGe) layer 30(in region 24) on top of silicon-carbide from silicon-carbide (SiC)layer 16 and insulated from the bulk silicon substrate 14 by thedielectric material (silicon dioxide (SiO₂) 64) that was filled in placeof the sacrificial silicon-germanium material of the layer 12. The finsfurther include fins 150 n made of silicon from silicon (Si) layer 18(in region 26) on top of silicon-carbide from silicon-carbide (SiC)layer 16 and insulated from the bulk silicon substrate 14 by thedielectric material (silicon dioxide (SiO₂) 64) that was filled in placeof the sacrificial silicon-germanium material of the layer 12. Thedielectric material under each fin 150 forms a dielectric pedestalregion 68 supporting the fin and insulating the fin from the bulksubstrate.

Conventional semiconductor processing as known in the art may thencontinue from the fins 150 defined as shown in FIG. 18 to finishfabrication of FinFET devices utilizing the fins 150.

The process for fin 150 formation disclosed herein possesses a number ofadvantages over prior art processes for bulk substrate supported FinFETdevices including: a) fin height is determined by an epitaxial growthprocess which results in more uniformly dimensioned fins in comparisonto conventional bulk processing which may rely, for example, on a SiO₂recess to define the fin dimensions; b) the fin 150 n for the n-channelFinFET devices is formed of silicon (from silicon (Si) layer 18) and thefin 150 p for the p-channel FinFET is formed of silicon-germanium (fromthe silicon-germanium (SiGe) layer 30) which promotes better transistorperformance with respect to both conductivity type transistors; c) thesource/drain regions of the fins 150 are isolated from the bulk siliconsubstrate 14 by dielectric material (from the silicon dioxide (SiO₂) 64material used to fill the apertures 60 left by the removal of thesacrificial silicon-germanium (SiGe) layer 12) so as to suppressjunction leakage; d) the process technique is well suited for use inaggressively scaled CMOS fabrication techniques at and below the 10 nmprocess node; and e) the process technique is compatible with both gatefirst and gate last integration processing for FinFET devices.

Although this process is somewhat complex, the process provides avaluable means to produce an Si n-channel FinFET and SiGe p-channelFinFET from a bulk wafer. Bulk wafer fabrication is attractive becauseof a lower price point. The steps of the method are common tosemiconductor fabrication and can be applied with limited cost.

The foregoing description has provided by way of exemplary andnon-limiting examples a full and informative description of theexemplary embodiment of this invention. However, various modificationsand adaptations may become apparent to those skilled in the relevantarts in view of the foregoing description, when read in conjunction withthe accompanying drawings and the appended claims. However, all such andsimilar modifications of the teachings of this invention will still fallwithin the scope of this invention as defined in the appended claims.

1. A method, comprising: on a substrate formed of a first semiconductormaterial and having a first region and a second region, depositing anoverlying sacrificial layer formed of a second semiconductor material;forming for the first region a region of first semiconductor materialover the sacrificial layer; forming for the second region a region ofsecond semiconductor material over the sacrificial layer; patterning theregion of first semiconductor material to define at least one first finof a FinFET transistor of a first conductivity type; patterning theregion of second semiconductor material to define at least one secondfin of a FinFET transistor of a second conductivity type; covering eachof the first and second fins with a cap and sidewall spacer; selectivelyremoving the sacrificial layer formed of the second semiconductormaterial to form an opening below each of the first and second fins,each first and second fin being supported by said sidewall spacer; andfilling the opening below each of the first and second fins with adielectric material so as to isolate the first and second fins from thesubstrate.
 2. The method of claim 1, wherein the first semiconductormaterial is silicon and the second semiconductor material issilicon-germanium.
 3. The method of claim 2, wherein the FinFETtransistor of the first conductivity type formed of the firstsemiconductor material is an n-channel device and wherein the FinFETtransistor of the second conductivity type formed of the secondsemiconductor material is a p-channel device.
 4. The method of claim 1,wherein the substrate is a bulk semiconductor substrate.
 5. The methodof claim 1, further comprising depositing an intermediate semiconductormaterial layer between the overlying sacrificial layer and each of theregion of first semiconductor material and region of secondsemiconductor material.
 6. The method of claim 5, wherein theintermediate semiconductor material layer is a silicon-carbide layer. 7.The method of claim 5, wherein each first fin comprises firstsemiconductor material over intermediate semiconductor material oversaid dielectric material, and each second fin comprises secondsemiconductor material over intermediate semiconductor material oversaid dielectric material.
 8. The method of claim 1, further comprisingremoving the cap and sidewall spacer to expose each of said first andsecond fins.
 9. The method of claim 1, wherein selectively removing thesacrificial layer formed of the second semiconductor material furtherforms openings adjacent each of the first and second fins, and whereinfilling further comprises filling the adjacent openings with thedielectric material to separate said fins from each other.
 10. Themethod of claim 1, further comprising defining a trench in the substratebetween adjacent fins, and wherein filling further comprises filling thetrench with the dielectric material.
 11. The method of claim 10, whereinselectively removing the sacrificial layer formed of the secondsemiconductor material further forms openings adjacent each of the firstand second fins, said trench in communication with said adjacentopenings, and wherein filling further comprises filling the adjacentopenings and trenches with the dielectric material.
 12. The method ofclaim 11, wherein covering further comprises lining each of the trencheswith said sidewall spacer.
 13. An apparatus, comprising: a substrateformed of a first semiconductor material and having a first region and asecond region; in the first region, a first dielectric pedestal with atrench on opposite sides of the first dielectric pedestal; in the secondregion, a second dielectric pedestal with a trench on opposite sides ofthe second dielectric pedestal; in the first region, a first fin of aFinFET transistor of a first conductivity type formed of a firstsemiconductor material over the first dielectric pedestal and insulatedfrom the substrate by the first dielectric pedestal; and in the secondregion, a second fin of a FinFET transistor of a second conductivitytype formed of a second semiconductor material over the seconddielectric pedestal and insulated from the substrate by the seconddielectric pedestal.
 14. The apparatus of claim 13, wherein saidtrenches on opposite sides of the first and second dielectric pedestalsfurther extend into said substrate to define corresponding substratepedestal regions supporting the dielectric pedestals.
 15. The apparatusof claim 14, further comprising a dielectric material at least partiallyfilling each of the trenches on opposite sides of the first and seconddielectric pedestals and at least partially filling each of the trenchesbetween the substrate pedestal regions.
 16. The apparatus of claim 15,further comprising a liner in said trenches between the substratepedestal regions and the at least partially filling dielectric material.17. The apparatus of claim 13, further comprising a dielectric materialat least partially filling each of the trenches on opposite sides of thefirst and second dielectric pedestals and a liner in said trenchesbetween the dielectric pedestals and the at least partially fillingdielectric material.
 18. The apparatus of claim 13, wherein thesubstrate is a bulk semiconductor substrate.
 19. The apparatus of claim13, further comprising an intermediate semiconductor material betweeneach of the first and second dielectric pedestals and the firstsemiconductor material of the first fin and second semiconductormaterial of the second fin, respectively.
 20. The apparatus of claim 19,wherein the intermediate semiconductor material is silicon-carbide. 21.The apparatus of claim 13 wherein the first semiconductor material issilicon and the second semiconductor material is silicon-germanium. 22.The apparatus of claim 21, wherein the FinFET transistor of the firstconductivity type formed of the first semiconductor material is ann-channel device and wherein the FinFET transistor of the secondconductivity type formed of the second semiconductor material is ap-channel device.